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1 ? fn6230.1 isl55141, isl55142, isl55143 high-speed 18v cmos comparators isl55141, isl55142, isl55143 integrated circuits are high-speed, wide input common-mode range comparators. they provide three-state window comparators in a high voltage cmos process (18v). each comparator has dual receive thresholds, cv a and cv b , for establishing minimum 1-v ih and maximum 0-v il voltage levels. these devices can accept inputs from a number of logic families, such as ttl, ecl, cmos, lvcmos, lvds and cml. two bits of output per comparator provide the test controller with qualification of a comparator input into three states. the two output bits work with a separate user supply to establish v oh , v ol levels compatibility with the system?s controller logic levels. fast propagation delay (9.5ns typical at 50mv overdrive) makes this family compatible with high-speed digital test systems. the 18v range enables the comparator input to operate over a wide input range. two references per input enable and three state digitalization of input with voltage swings of up to 13v common mode. the operating frequency of these devices is typically 65mhz. high voltage cmos process makes these devices ideal for large voltage swing applications, such as special test voltages levels associated wi th flash devices or power supervision applications and ma y avoid the need for test bus isolation relay(s). functional block diagram features ? 18v i/o range ? 65mhz operation ? 9.5ns typical propagation delay ? programmable input thresholds ? user defined comparator outputllevels ? common-mode range includes negative rails ? small footprints in qfn packages ? power-down current <10a ? pb-free (rohs compliant) applications ? burn in ate ? low cost ate ? fast supervisory power control ? instrumentation cv ax cv bx v inpx q ax v oh v ol v cc v ee v oh v ol v cc v ee q bx dual level comparator - receivers note: x denotes 1, 2 or 4 channels for isl55141, isl55142 and isl55143, respectively ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # isl55141irz* 55 141irz -40 to +85 16 ld qfn l16.4x4a isl55141ivz* 55141 ivz -40 to +85 14 ld tssop m14.173 isl55142irz* 55142 irz -40 to +85 20 ld qfn l20.5x5 ISL55142IVZ* 55142 ivz -40 to +85 20 ld tssop m20.173 isl55143irz* 55143 irz -40 to +85 36 ld tqfn l36.6x6 *add ?-t? suffix for tape and reel. please refer to tb347 for details on reel specifications. note: these intersil pb-free pl astic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow te mperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet october 30, 2008 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2008. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6230.1 october 30, 2008 pinouts nc 20 19 18 17 16 36 35 34 33 cv a0 v inp0 cv b0 cv b1 nc nc v cc v ee 32 31 v cc v ee v inp1 cva1 v cc v ee nc cv b0 v inp0 cv a0 cv b1 v inp1 cv a1 1 2 3 4 5 1 2 3 4 5 6 15 14 13 12 11 27 26 25 24 23 22 pd v ee v cc v oh v ol nc q a0 q b0 q a1 q b1 q a2 678910 10 11 12 13 14 15 q a0 q b0 q a1 q b1 nc v oh v ol v oh v ol v ee v cc 7 8 q b2 q a3 16 17 cv a3 v inp3 cv b2 v inp2 21 20 30 29 nc nc nc 16 15 14 13 v ee nc pd nc cv b v inp cv a 1 2 3 4 12 11 10 9 nc nc q a q b 5678 v ol v oh v ee v cc 9 q b3 18 cv b3 cv a2 19 28 pd 18 19 20 13 17 16 15 14 1 2 3 4 5 7 6 8 cv b0 v inp0 cv a0 pd v ee v cc v ol v oh cv b1 cv a1 nc v cc v ee nc nc v inp1 12 9 q a0 q b1 11 10 q b0 q a1 isl55141 single device (16 ld 4x4 qfn) top view isl55142 single device (20 ld 5x5 qfn) top view isl55141 (14 ld tssop) top view isl55143 quad device (36 ld6x6 tqfn) top view 12 13 14 11 10 9 8 1 2 3 4 5 7 6 v ee nc nc q a q b v ol v oh pd cv b v inp cv a v cc v ee nc isl55142 (20 ld tssop) top view isl55141, isl55142, isl55143
3 fn6230.1 october 30, 2008 pin descriptions pin function v ee negative supply input q ax channel a, cv ax reference driven. comparator output. q bx channel b, cv bx reference driven. comparator output. v ol comparator output logic low supply. unbuffered analog input that sets all q ax , q bx ?low? voltage level. v oh comparator output logic high supply. unbuffered analog input that sets all q ax , q bx ?high? voltage level. vcc positive supply input. cv ax channel a comparator reference analog input. v inpx window comparator input. common to both channel ax and channel bx. cv bx channel b comparator reference analog input. pd power-down logic input (connect to v ee if not used for power-down). nc no internal connection. table 1. cv a -q a and cv b -q b basic comparator truth table input outputs* v inpx q ax q bx cv bx 01 >cv ax cv ax >cv bx 11 * when q ax /q bx = 1, output is connect to v oh * when q ax /q bx = 0, output is connect to v ol isl55141, isl55142, isl55143
4 fn6230.1 october 30, 2008 absolute maximum rati ngs thermal information v cc to v ee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 19v input voltages pd, cv ax , cv bx , v inpx , v oh , v ol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (v ee -0.5v) to (v cc +0.5v) output voltage q ax , q bx . . . . . . . . . . . . . . . . . . . . . (v ol -0.5v) to (v oh +0.5v) thermal resistance (typical, note 1, 2) ja (c/w) 16 ld qfn package. . . . . . . . . . . . . . . . . . . . . . . . . 75 14 ld tssop package . . . . . . . . . . . . . . . . . . . . . . 90 20 ld qfn package. . . . . . . . . . . . . . . . . . . . . . . . . 65 20 ld tssop package . . . . . . . . . . . . . . . . . . . . . . 80 36 ld tqfn package . . . . . . . . . . . . . . . . . . . . . . . 45 maximum junctin temperature (plastic plackage) . . . 150 maximum storage temperature range . . . . . . . . . . . -65c to 150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 1. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. 2. device temperature is closely tied to dat a-rates, driver loads and overall pin acti vity. review power dissipation considerati ons for more information. recommended operating conditions parameter symbol min typ max units device power v cc -v ee 10 15 18 v comparator output high rail v oh v ee +1 v cc -0.5 v comparator output low rail v ol v ee +0.5 v ee +6 v common mode input voltage range v cm v ee v cc -5 v ambient temperature t a -40 27 +85 c junction temperature t j +125 c electrical specifications test conditions: v cc = 12v, v ee = -3v, v oh = 5v, v ol = 0v, pd = v ee , c load = 15pf , t a = 25c, unless otherwise specified. parameter symbol test conditions min (note 7) typ max (note 7) units dc characteristics input offset voltage v os cv ax = cv bx = 1.5v -50 50 mv input bias current i bias v inpx - cv (a/b)x = 5v 10 25 na power-down current i pd pd = v cc 825 a power-down time (note 5) t pd 10 s power-up time (note 5) t pu 15 s timing characteristics propagation delay t pd 4.0 9.5 15 ns rise time (note 5) t r 1.4 ns fall time (note 5) t f 1.5 ns propagation delay mismatch t pd 0.5 2 ns maximum operating frequency f maxr symmetry 50% 65 mhz min pulse width t widr 7.7 ns comparator input input current i in v inpx = v cc or v ee -100 0 100 na input capacitance (note 5) c in 2.5 pf isl55141, isl55142, isl55143
5 fn6230.1 october 30, 2008 digital outputs q ax , q bx output resistance routr 18 27 37 output logic high voltage v oh v oh = 5v, i source = 1ma 4.9 4.95 5.0 v output logic low voltage v ol v ol = 0v, i sink = 1ma 0.00 0.05 0.1 v power supplies, static conditions positive supply dc current/comparator i cc no input data +8.25 12.5 ma negative supply current/comparator i ee no input data -12.5 -8.25 ma total power dissipation/comparator p (note 6) input data at 40mhz 670 mw notes: 3. lab characterization, room temperature, timing parameters matched stimulus/loads, channel-to- channel skew < 500ps, 1ns maximu m by design 4. note about i cc measurement input can approach 140ma (single comparator) at maximum pattern rates 5. limits should be considered ty pical and are not production tested. 6. total power dissipation per comparator can be approximately calculated from the following: p = (v cc -v ee )*8.25mw + 90pf*(v cc -v ee )^2*f + c l *(v cc -v ee )^2*f, where f is the operating frequency and c l is the load capacitance. because the isl55142 has two comparators, the power dissipation w ould be twice of p calculated from this equation. the isl55143 would be four times p. 7. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. test circuits and waveforms figure 1. comparator propagation delay and transition time measurement points figure 2. three-state window comparator fundamentals electrical specifications test conditions: v cc = 12v, v ee = -3v, v oh = 5v, v ol = 0v, pd = v ee , c load = 15pf , t a = 25c, unless otherwise specified. (continued) parameter symbol test conditions min (note 7) typ max (note 7) units q ax , q bx 400mv 0v t pdlh v oh ( v h ) v ol ( v l ) 50% 50% t pdhl v inpx t r t f data = 1 data = 0 + - + - v inp q a q b cv a 2.4v cv b 0.4v v cc v ee although there is no electrical difference between the cv a and cv b inputs, if one defines cv a as being the high threshold and cv b being the low threshold, it becomes easier to understand the utilization of a dual threshold comparator. essentially this enables the qualification of an incoming signal into three states. in figure 2, the three states are valid low <0.4v, no-man?s-land (between 0.4 and 2.4v), valid high >2.4v. table 1 shows how the q a /q b truth table would be utilized in the real world. table 1. q a /q b truth table v inp q a q b comment <0.4v 0 0 valid 0 >0.4 and <2.4v 0 1 invalid >2.4v 1 1 valid 1 isl55141, isl55142, isl55143
6 fn6230.1 october 30, 2008 application information the isl55141, isl55142, isl55143 provide 1, 2 and 4 dual threshold, three-state window comparator(s) in tssop or qfn footprints. they offer a combination of speed (10ns tpd and wide voltage range (18v). this product directly addresses the need for unique common-mode characteristics while suppl ying a power-down feature. figures 3 and 4 show the stimulus setup and measurement points for an example propagation delay measurement. typical room temperature results are displayed in figure 11. figure 4 shows a v inp range of 50mv. in figure 11 the offset is increased in the horizontal axis from 50mv above and below the reference (1.5v) up to 2.5v above and below the 1.5v reference. two lines are displayed in figure 11. one represents the rising-to-rising delay (t pdlh ) and the other the falling-to-falling delay (t pdhl ). comparator features these three-state window comparators feature high output current capability, and user defined high and low output levels to interface with a wide variety of logic families. each receiver comprises two comparators and each comparator has an independent threshold level input, making it easy to implement (minimum1-v ih )/(maximum 0-v il ) logic level comparator functions. the cv ax and cv bx pins set the threshold levels of the a and b comparators respectively. v oh and v ol set all the comparator output levels, and v oh must be more positive than v ol . these two inputs are unbuffered supply pins, so the sources driv ing these pins must provide adequate current for the expected load. v oh and v ol typically connect to the power supplies of the logic device driven by the comparator outputs. the truth table for the receivers is given in table 1. receiver outputs are not tri-statable, and do not incorporate any on-chip short circuit current protection. momentary short circuits to gnd, or any supply voltage, will not cause permanent damage, but care must be taken to avoid longer duration short circuits. if tolerable to the application, current limiting resistors can be inserted in series with the q ax and q bx outputs to protect the receiver outputs fr om damage due to overcurrent conditions. power-down features the isl55141, isl55142, isl55143 pd pin provides a means of reducing current cons umption when the device is not in use. supply currents fall from ~7ma to less than 10a in the power-down mode. the device requires approximately 10s to power-down and 15s to power-up. power supply bypassing and printed circuit board layout as with any high frequency device, good printed circuit board layout is necessary for optimum performance. ground plane construction is highly recommended, lead lengths should be as short as possible, and the power supply pins must be well bypassed to reduce the risk of oscillation. for normal single supply operation, where the v ee pin is connected to ground, one 0.1f ceramic capacitor should be placed from the v cc pin to ground. a 4.7f tantalum capacitor should then be connected from the v cc pin to ground. this same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. figure 3. t pd receiver switching test circuit figure 4. t pd receiver propagation delay measurement points test circuits and waveforms (continued) + - + - v inp q a q b +11 v cc -3 v ee cv a 1.5v cv b 1.5v + 5v-v oh v ol q x 50mv -50mv t pdlh v oh ( 5v) v ol ( 0v) 50% 50% t pdhl v inp 1.5v 1.5v cv a = cv b = 1.5v isl55141, isl55142, isl55143
7 fn6230.1 october 30, 2008 power dissipation considerations specifying continuous data rates, driver loads and driver level amplitudes are key in determining power supply requirements as well as dissipation/cooling necessities. driver output patterns also impact these needs. the faster the pin activity, the greater the need to supply current and remove heat. the maximum power dissipation allowed in a package is determined according to equation 1. where: ?t jmax = maximum junction temperature ?t amax = maximum ambient temperature ? ja = thermal resistance of the package ?p dmax = maximum power dissipation in the package approximate power dissipation (typ) p = n*[(v cc -v ee )*8.25mw + 90pf*(v cc -v ee )^2*f + cl*(v oh -v ol )^2*f] where: n is the number of comparators in the chip (1 for isl55141, 2 for isl55142 and 4 for isl55143). (f) is the operating frequency. cl is the load capacitor. the power dissipation calculated from the above formula may have an error of 20 to 25%. the maximum power dissipation actually produced by an ic is the total quiescent supply current times the total power supply voltage, plus the power in the ic due to the loads. power also depends on the number of channels changing state and frequency of operation. the extent of continuous active pattern generation/reception will greatly affect dissipation requirements. the user should evaluate various heat sink/cooling options in order to control the ambient temperature part of the equation. this is especially tr ue if the user?s applications require continuous, high-speed operation. note: the reader is cautioned against assuming the same level of thermal performance in actual applications. a careful inspection of conditions in your application should be conducted. power supply information circuit design must always take into account the internal eos/esd protection structure of the device. important note: the qfn package metal plane is used for heat sinking of the device. it is electrically connected to the negative supply potential (v ee ). if v ee is tied to ground, the thermal pad can be connected to ground. otherwise, the thermal pad (v ee ) must be isolated from other power planes. power supply sequencing the isl55141, isl55142, isl55143 reference every supply with respect to v ee . therefore, apply v ee , v ol then v cc followed by the cv a and cv b supplies. the comparator v inp pin should not exceed v ee or v cc during power-up. in cases where inputs may exceed voltage rails during power-up, series resistance should be employed to safeguard eos to the esd protection diodes. p dmax t jmax - t amax ja -------------------------------------------- - = (eq. 1) v ee v oh v inp optional protection v cc diode optional protection diode q a q b v ol cv a cv b isl55141, isl55142, isl55143
8 fn6230.1 october 30, 2008 typical performance curves device installed on intersil isl55141, isl55142, isl55143 evaluation boards. figure 5. isl55141, isl55142, isl55143 quiescent current figure 6. isl55141 i cc vs frequency @ 10v, 14v, and 18v figure 7. isl55142 i cc 1 and 2 channels active figure 8. isl55143 i cc 1, 2, 3, 4 channels active figure 9. isl55142 2-channel i cc @ 10v, 14v, and 18v figure 10. isl55143 4-channel i cc @ 10v, 14v, and 18v 30.0 27.0 24.0 21.0 18.0 15.0 12.0 09.0 06.0 03.0 00.0 10 12 14 16 18 v cc - v ee voltage isl55143 isl55142 isl55141 i cc (ma) 60 54 48 42 36 30 24 18 12 6 0 3200 1600 800 400 200 100 50 25 v inp square wave period in ns v cc = 10v i cc (ma) v cc = 18v v cc = 14v 80 72 64 56 48 40 32 24 16 8 0 3200 1600 800 400 200 100 50 25 v inp square wave period in ns 2 channels 1 channel i cc (ma) 200 180 160 140 120 100 80 60 40 20 0 3200 1600 800 400 200 100 50 25 v inp square wave period in ns 4 channels 1 channel i cc (ma) 2 channel 3 channel 100 90 80 70 60 50 40 30 20 10 0 3200 1600 800 400 200 100 50 25 v inp square wave period in ns i cc (ma) v cc = 10v v cc = 14v v cc = 18v 250 225 200 175 150 125 100 75 50 25 0 3200 1600 800 400 200 100 50 25 v inp square wave period in ns i cc (ma) v cc = 18v v cc = 14v v cc = 10v isl55141, isl55142, isl55143
9 fn6230.1 october 30, 2008 figure 11. propagation delay @ 14v v cc -v ee figure 12. minimum pulse width response typical performance curves device installed on intersil isl55141, isl55142, isl55143 evaluation boards. (continued) 15.0 13.5 12.0 10.5 9.0 7.5 6.0 4.5 3.0 1.5 0 0.05 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 v inp input offset 1.5 volt reference -tpd delay delay (ns) +tpd delay t pdlh t pdhl 0 0 10ns/div 0.5v/div 1.0v/div v cc 15.0 v ee - 3.0 isl55141, isl55142, isl55143
10 fn6230.1 october 30, 2008 isl55141, isl55142, isl55143 quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) l16.4x4a 16 lead quad flat no-lead plastic package (compliant to jedec mo-220-vggd-10) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.18 0.25 0.30 5, 8 d 4.00 bsc - d1 3.75 bsc 9 d2 2.30 2.40 2.55 7, 8 e 4.00 bsc - e1 3.75 bsc 9 e2 2.30 2.40 2.55 7, 8 e 0.50 bsc - k0.25 - - - l 0.30 0.40 0.50 8 l1 - - 0.15 10 n162 nd 4 3 ne 4 3 p- -0.609 --129 rev. 2 3/06 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are prov ided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.
11 fn6230.1 october 30, 2008 isl55141, isl55142, isl55143 thin shrink small outlin e plastic packages (tssop) index area e1 d n 123 -b- 0.10(0.004) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) c e 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-153-ac, issue e. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dam bar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimen- sion at maximum material conditi on. minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. (angles in degrees) 0.05(0.002) m14.173 14 lead thin shrink small outline plastic package symbol inches millimeters notes min max min max a - 0.047 - 1.20 - a1 0.002 0.006 0.05 0.15 - a2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - d 0.195 0.199 4.95 5.05 3 e1 0.169 0.177 4.30 4.50 4 e 0.026 bsc 0.65 bsc - e 0.246 0.256 6.25 6.50 - l 0.0177 0.0295 0.45 0.75 6 n14 147 0 o 8 o 0 o 8 o - rev. 2 4/06
12 fn6230.1 october 30, 2008 isl55141, isl55142, isl55143 quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) l20.5x5 20 lead quad flat no-lead plastic package symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - 0.02 0.05 - a2 - 0.65 1.00 9 a3 0.20 ref 9 b 0.23 0.30 0.38 5, 8 d 5.00 bsc - d1 4.75 bsc 9 d2 2.95 3.10 3.25 7, 8 e 5.00 bsc - e1 4.75 bsc 9 e2 2.95 3.10 3.25 7, 8 e 0.65 bsc - k0.20 - - - l 0.35 0.60 0.75 8 n202 nd 5 3 ne 5 3 p- -0.609 --129 rev. 4 11/04 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. compliant to jedec mo-220vhhc issue i except for the "b" dimension.
13 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6230.1 october 30, 2008 isl55141, isl55142, isl55143 thin shrink small outlin e plastic packages (tssop) index area e1 d n 123 -b- 0.10(0.004) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) c e 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-153-ac, issue e. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dam bar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimen- sion at maximum material conditi on. minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. (angles in degrees) 0.05(0.002) m20.173 20 lead thin shrink small outline plastic package symbol inches millimeters notes min max min max a - 0.047 - 1.20 - a1 0.002 0.006 0.05 0.15 - a2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - d 0.252 0.260 6.40 6.60 3 e1 0.169 0.177 4.30 4.50 4 e 0.026 bsc 0.65 bsc - e 0.246 0.256 6.25 6.50 - l 0.0177 0.0295 0.45 0.75 6 n20 207 0 o 8 o 0 o 8 o - rev. 1 6/98
14 fn6230.1 october 30, 2008 isl55141, isl55142, isl55143 package outline drawing l36.6x6 36 lead thin quad flat no-lead plastic package rev 5, 08/08 bottom view side view typical recommended land pattern top view dimensioning and tolerancing conform to amsey14.5m-1994. dimension applies to the metallized terminal and is measured the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. tiebar shown (if present) is a non-functional feature. unless otherwise specified, tolerance : decimal 0.05 4. 5. 6. 3. 2. dimensions are in millimeters. 1. located within the zone indicated. the pin #1 indentifier may be either a mold or mark feature. c detail "x" 0.2 ref 0.05 max. 0.00 min. 5 6.00 a b 6.00 (4x) 0.15 6 pin 1 index area 28 pin #1 index area 36 32 x 0.50 4.15 +0.10/-0.15 9 1 27 19 18 36 x 0.55 0.10 10 6 4x 4.00 max 0.80 see detail "x" 0.08 0.10 c c c ( 5.65 ) ( 4.15) (36x 0.75) (36 x .25) ( 32 x 0.50) ( 5.65 ) ( 4 x 4.00) exp. dap. ( 4.15) exp. dap. 0.10 36 x 0.25 +0.05/-.07 a m c b 4

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